Reference is made to FIG. 1 showing a conventional memory cell 10 for a non-volatile memory of the electrically-erasable programmable read only memory (EEPROM) type. The cell 10 is formed of two transistors coupled in series with each other between a bit line (BL) and a source node (S). A first transistor of the cell 10 is referred to as a select transistor 12. A second transistor of the cell 10 is referred to as a floating gate transistor 14. The transistors 12 and 14 are field effect transistor (FET) devices, preferably of the n conductivity type. The source-drain paths of the two transistors 12 and 14 are connected in series. A first conduction node (source or drain) of transistor 12 is connected to the bit line BL and a second conduction node (drain or source) of transistor 12 is connected to an intermediate node 16. A first conduction node (source or drain) of transistor 14 is connected to the intermediate node 16 and a second conduction node (drain or source) of transistor 14 is connected to a source (S) line. The gate of the select transistor 12 is coupled to a word line (WL) and the gate of the floating gate transistor is coupled to a control gate (CG) line.
Reference is now made to FIG. 2. To form a memory 20, a plurality of the memory cells 10 (see, FIG. 1) are arranged in an array format to form a plurality of columns 22 and a plurality of rows 24. The first conduction nodes of transistors 12 in a given column 22 are connected to a same bit line BL. The second conduction nodes of transistors 14 for an adjacent pair of cells 10 in adjacent rows 24 are connected to a common source node S line. The gates of the select transistors 12 for the cells 10 in a given row 24 are coupled to a same word line WL. Likewise, the gates of the floating gate transistors 14 for the cells 10 in that same given row 24 are coupled to a same control gate CG line. The parenthetical number (for example, (0) or (1)) after the references in FIG. 2 indicates the identification of the particular row or column.
The portion of the memory 20 illustrated in FIG. 2 includes four cells 10 and thus is configured to store four bits of data (with two columns using bit lines BL(0) and BL(1) and two rows with word lines WL(0) and WL(1) and control gate lines CG(0) and CG(1)). The “ . . . ” designations in the illustration are intended to show that the memory 20 may include many more cells extending in horizontal and vertical directions for a number of rows and columns.
Data retention in the memory 20 is a significant concern. It is well known to those skilled in the art that the floating gate transistor 14 in a given memory cell 10 may, over time, degrade to the point where it does not consistently operate properly or may even fail completely. The floating gate transistor 14 typically fails because it loses its ability to store (or maintain storage over time of) charge. In this condition, the cell 10 may be said to have an undetermined logic state (centered sensing) or may always read in a same state (where the sensing is not centered).
To address this issue, it is known in the art for the memory 20 to include error correction capabilities. It is also known in the art for the memory 20 to include redundant rows and columns which may be utilized in place of a row or column containing a failed or defective cell. It is also known in the art to provide redundant cells, for example, two cells per bit, so that if one cell is defective the other cell can still provide the memory storage operation. Memory designs which utilize multiple cells per bit (in either a serial connection or parallel connection) have a number of known drawbacks.